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Technical Support

RT and Embedded SW and FW developing
  • API Architecture developing
  • C/Assembly solutions for overall product efficiency
  • Low-level drivers and BSP developing
  • Modern RISC and DSP platforms covered
SW and FW solutions optimizing
  • GP CPU SIMD (ARM NEON, MIPS MSA) vectorized optimizations using compiler, intrinsic functions and deep Assembly-level optimization
  • MCU FW and SW optimization using compiler, intrinsic functions and deep Assembly-level optimization
  • Assembly-level optimization of DSP solutions
Problem root cause analysis
Solutions efficiency analysis and improvment
Support of multiple vendors

Technology Training

Courses for engineers and managers

System Architecture
  • Bus standards, multi-layer bus architecture
  • HW/SW partitioning
  • Embedded SW development - tools and optimization approaches
DSP architecture and code optimization. 
  • Fixed point and Floating point computation
  • Superscalar (VLIW) and multiissue parallel architecture
  • Vectored (SIMD) architecture
  • Multithreading (SIMT) architecure (GPU)
ARM and ARM-based application processors
  • ARMv7/v8 Architecture
  • Cortex A/R/M architecture, programming and SW optimization
  • NXP Kinetis Family
  • STMicroelectronics  STM32 Family

Consulting

New SOC/ASIC Development assistance
  • MRD and PRD analysis
  • SOC/ASIC architecture specifications
  • Homogeneous and Heterogeneous multiporcessor architecture
  • HW/SW system partitioning
  • Multibus interconnect layout and optimal system arbitration
  • Bandwidth estimation and performance optimization
New CPU and Data Processing engines architecture design
  • Pipelined engines
  • Programmable and hardwired processing units
  • ISA definition
  • DSP, RISC, Vectorized, Cluster, GPU architectures